1. Field of the Invention
The present invention relates to delay adjustment between a memory and a memory controller, and particularly to delay adjustment between a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) and a memory controller.
2. Description of Related Art
A DDR SDRAM is a memory including a high-speed transfer function. In particular, the DDR SDRAM can read and write data on both the rising and falling edges of the clock signal for synchronization between circuits. That is to say, the DDR SDRAM inputs and outputs data with twice the frequency of an external clock. Therefore, the DDR SDRAM has a narrower data width (width of determined data), at which data can be reliably read, than that of SDR SDRAM. It is also necessary to notify a timing to read data output from the DDR SDRAM correctly. Thus, the DDR SDRAM uses a data strobe signal (DQS). The data strobe signal is a signal to notify a timing to transfer data. Specifically, the DDR SDRAM outputs a data signal (DQ) and the data strobe signal at the same time. A requestor requesting data transfer receives the data signal and the data strobe signal in response to issuance of a read command. The requestor retrieves data from the data signal in accordance with the data strobe signal. For the purpose of this operation, a memory controller is employed. The memory controller is placed between the memory and the requestor, and includes general functions to control the operation of memory access.
When the requestor issues the read command to the memory, a difference in time (flight time) for data to reach the requestor occurs depending on the length of a line between the memory and the memory controller. This makes it difficult for the requestor to determine the timing to retrieve data. Particularly in the DDR SDRAM, a higher read-operation speed is attained, so the flight time between the memory and the memory controller with respect to an operation clock cycle cannot be ignored.
As a result, it is necessary to provide the memory controller having a configuration in which a delay of the flight time is considered to determine a timing to receive the data strobe signal. The flight time varies depending on implementation conditions, such as the length of a line between the memory and the memory controller. For this reason, the reception timing is not determined uniquely in the process of designing the memory controller. It is necessary to incorporate a function (for example, a circuit) for dealing with a certain range of flight time in the memory controller.
For example, Japanese Unexamined Patent Application Publication No. 2005-276396 discloses a technique of adjusting a delay time using an expected value at initialization of a device. In the technique, a calibration pattern is formed in a memory, and PASS/FAIL determination is performed using the formed pattern as the expected value at the initialization of the device. Then, the delay time is adjusted to be optimized based on the determination result. FIG. 6 is a circuit diagram showing a configuration of a memory interface control circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-276396.
The circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-276396 is a circuit which performs the functions as noted below. The circuit generates in the inside thereof a timing of retrieving the DQS, actually performs read and write operation on the DRAM, and checks an expectation value in order to confirm whether retrieved data is correct or not. The circuit selects an optimal timing after repetition of generating the timing of retrieving the DQS while gradually shifting the timing of retrieving the DQS.
Japanese Unexamined Patent Application Publication No. 2003-223786 discloses a circuit incorporating a comparator to detect a timing of starting point of preamble. The timing of starting point of preamble indicates a change from an impedance state to a low level state. FIG. 7 shows a data strobe receiver disclosed in Japanese Unexamined Patent Application Publication No. 2003-223786. Further, Japanese Unexamined Patent Application Publication No. 2008-103013 discloses a technique of eliminating unstable operation caused by a variation in delay of the data strobe signal. FIG. 8 is a diagram showing a configuration of a memory read controller disclosed in Japanese Unexamined Patent Application Publication No. 2008-103013. The memory read controller controls a pull up circuit 11s to pull-up the data strobe signal when a read request signal turns active. Upon receiving preamble, a signal changes from high level to low level. Input of the DQS is enabled valid by an enable signal of a control circuit 14s. Then, the input of DQS is disabled by the enable signal of the control circuit 14s after edges of the DQS signal are counted by the number of burst lengths.
The circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-276396 requires a circuit to preliminarily write a calibration pattern to a memory, and a comparison circuit to compare data read from a memory, resulting in an increase in circuit size.
The size of control circuit disclosed in Japanese Unexamined Patent Application Publication No. 2003-223786 becomes large, because the circuit needs to be added with a comparator for requesting independent 2nd Vref and a voltage supply. The control circuits disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-223786 and 2008-103013 also detect the timing of retrieving the DQS signal, but do not recognize the flight time. In the configuration in which the flight time is not recognized, it is necessary to reset the clock in order to transfer data to the subsequent-stage circuit (requestor). In these cases, the control circuits use a FIFO, for example, which results in an increase in circuit size.
As described above, the flight time between the memory and the memory controller cannot be calculated in design phase because the flight time varies depending on the length of a line. Therefore, the memory controller requires a circuit to adjust the flight time.